While advances in silicon (Si) technology continue to revolutionize the development of micro and nano electronics, the semiconductor industry is conducting significant research in the heterogeneous integration of compound semiconductors with Si substrates for the development of high-speed electronic and optoelectronic devices. For example, one class of compound semiconductors referred to as “III-V compound semiconductors” include at least one element from each of Group III and Group V of the periodic table of elements. Examples of III-V compound semiconductors include, but are not limited to, GaAs (Gallium Arsenide), InP (Indium Phosphide), InGaAs (Indium Gallium Arsenide), InAs (Indium Arsenide), GaP (Gallium Phosphide), InSb (Indium Antimonide), GaSb (Gallium Antimonide), GaN (Gallium Nitride), and AlInP (Aluminum Indium Phosphide).
FinFET technology is an emerging semiconductor technology being developed to provide effective scaling solutions for field effect transistor (FET) fabrication at, and below, the 22 nm node, using heterogeneous integration of compound semiconductors. FinFET structures include one or more narrow semiconductor fin structures, wherein each semiconductor fin structure is gated on at least two sides thereof. The semiconductor fin structures of FinFET devices can be formed by growing III-V compound semiconductors on silicon substrates using ART (aspect ratio trapping) techniques. ART enables selective epitaxy of III-V compound semiconductor material to fill high aspect ratio trenches formed in an insulating layer, to thereby form high quality active channel layers of III-V material for FinFET devices. Indeed, the high aspect ratio trenches serve to trap threading dislocations at the bottom of the trenches during epitaxial growth, thereby reducing the dislocation density of lattice mismatched compound semiconductor materials (e.g., III-V materials) grown on silicon.
ART requires a CMP (chemical and mechanical polishing) step to etch away excess epitaxial material which results from the ART process and produce smooth surface morphologies. However, these techniques are uneconomical as there is a significant amount of costly precursor material (e.g., III-V material) used to overgrow the epitaxial layers to facilitate CMP, which is ultimately etched away via the CMP process and wasted. Moreover, compound semiconductor materials such as III-V materials include toxic materials (e.g., arsenic). Therefore, conventional methods that use CMP to etch away excess epitaxial III-V material, for example, result in the generator of toxic gases and waste (e.g., arsenic in waste water), which is environmentally unfriendly.